Abstract-Distance prediction algorithms use O(N ) Round Trip Time (RTT) measurements to predict the N2 RTTs among N nodes. Distance prediction can be applied to improve the performance of a wide variety of Internet applications: for instance, to guide the selection of a download server from multiple replicas, or to guide the construction of overlay networks or multicast trees. Although the accuracy of existing prediction algorithms has been extensively compared using the relative prediction error metric, their impact on applications has not been systematically studied.In this paper, we consider distance prediction algorithms from an application's perspective to answer the following questions: (1) Are existing prediction algorithms adequate for the applications? (2) Is there a significant performance difference between the different prediction algorithms, and which is the best from the application perspective? (3) How does the prediction error propagate to affect the user perceived application performance? (4) How can we address the fundamental limitation (i.e., inaccuracy) of distance prediction algorithms?We systematically experiment with three types of representative applications (overlay multicast, server selection, and overlay construction), three distance prediction algorithms (GNP, IDES, and the triangulated heuristic), and three real-world distance datasets (King, PlanetLab, and AMP). We find that, although using prediction can improve the performance of these applications, the achieved performance can be dramatically worse than the optimal case where the real distances are known. We formulate statistical models to explain this performance gap. In addition, we explore various techniques to improve the prediction accuracy and the performance of prediction-based applications. We find that selectively conducting a small number of measurements based on prediction-based screening is most effective.
Vertical integration technology offers numerous advantages over conventional structures. Double-gate transistors can be easily fabricated for better device characteristics, and multiple device layers can be vertically stacked for better interconnect performance. In the paper, the authors explore the suitable device structures and interconnect architectures for multidevice-layer three-dimensional (3D) integrated circuits and study how 3D silicon-on-insulator (SOI) circuits can better meet the performance and power dissipation requirements projected by International Technology Roadmap for Semiconductors (ITRS) for future technology generations. Results demonstrate that double-gate SOI circuits can achieve as much as 20% performance gain and 30% power delay product reduction over single-gate SOI. More important, for interconnectdominated circuits, 3D integration offers significant performance improvement. Compared to 2D integration, most 3D circuits can be clocked at much higher frequencies (double or even triple). 3D circuits, with suitable SOI device structures, can be a viable solution for future low-power high-performance applications.
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