There currently lacks a crew systems engineering approach for integrating the crew station within the total aircraft system. To address this problem, ONT (Code 212) and the Naval Air Systems Command (NAVAIR 5 3 1fPMA 202) initiated the Advanced Technology Crew Station (ATCS) program at the Naval Air Development Center (NADC). ATCS involves multiple Navy laboratories, McDonnell Douglas, and Boeing Military Aircraft.
One of the major Joint Integrated Avionics Working Group (JIAWG) objectives is to ensure that reliable and maintainable systems can be built from JIAWG common modules. To facilitate attaining this objective, a JIAWG Diagnostic Concept and Initiative are discussed. A three-level diagnostic concept is described in terms of system, system element, and module management requirements. The corresponding JIAWG initiative is also discussed with respect to requirements for developing a common methodology for deriving fault coverage metrics as well as proof of concept demonstrations necessary to show compliance with JIAWG requirements.
An experimental distributed microprocessor subsystem is currently under development at the Naval Air Development Center as a vehicle to investigate distributed processing concepts with respect to replacing larger computers with networks of microprocessors at the subsystem or node level. Major benefits being exploited include increased performance, flexibility, system availability, and survivability by use of multiple processing elements with reduced cost, size, weight and power consumption. This paper concentrates on defining the distributed processing concept in terms of control primitives, variables, and structures and their use in performing a decomposed DFT (Discrete Fourier Transform) application function. The DFT was chosen as an experimental application to investigate distributed processing concepts because of its highly regular and decomposable structure for concurrent execution. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described.The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8-bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time. For discussion purposes, five of the processors are designated as slaves and one as a master where each slave contains an identical copy of a control executive and application program tasks. In actual operation, the slave processors cooperate to compute the DFT where the master provides external input, output, and control functions. With this implementation, commands to perform a DFT iteration are provided through the master.It is expected that this concept will be tested and demonstrated on a laboratory model by the end of 1980. Evaluations will concentrate on areas such as performance comparisons based on varying the number of processors and bus contention factors as a function of local processing and common data base access times. Future work will focus on fault tolerant techniques that can be directly implemented and evaluated on the baseline laboratory model.
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