Fully Depleted Silicon-On-Insulator (FDSOI) technology is a strong competitor in particular for RF applications, providing high performance at low manufacturing cost. In this technology, PFET devices utilize an epitaxially grown pFET raised source/drain (pRSD). However, the pRSD structure adds to the parasitic capacitance to the gate which is a detractor of RF performance. We demonstrate a faceted epitaxial RSD process that reduces this parasitic capacitance (CMiller) by up to -25% and further improves the already high RF pFET fmax by +18%. In addition, we show improved defectivity (-80% non-selective growth defect count reduction), and reduced within-wafer CMiller variability (1-s reduced by -42%). All of these make faceted pRSD a powerful technique to significantly improve device performance in FDSOI.
Causes of high-ohmic contact resistance were explored by analyzing several integrated circuit samples with an ion microprobe. Presence of oxide and dopant depletion at the interface were indicated. Mapping of oxygen vs depth through an oxide revealed that not only the elements present, but also the layered structure of the material could be observed. The possible production of artifacts due to electrostatic charges on the surfaces of a sample was noted.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.