No abstract

A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed.Index Terms-Logarithm approximation, Mitchell's error correction, piecewise linear approximation.

Abstract-We propose a generalization of the matched subspace filters for the detection of unknown signals in a background of non-Gaussian and non-independent noise. The generalization is based on a modification of the Rao test by including a linear transformation derived from Independent Component Analysis (ICA). Receiver Operating Characteristic (ROC) curves computed for simulated examples illustrate the significant improvement achieved with the generalized solution.Index Terms-Rao test, matched subspace filter, non-Gaussian noise, ICA.

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan (Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

No abstract