This paper describes a 155MHz clock recovery phase locked loop (PLL) for use in fiber optic serial data communication systems. The PLL incorporates a low jitter voltage controlled ring oscillator. Some of the inherent limitations of the ring architecture, as well as design techniques for dealing with those limitations, are discussed.The PLL chip has been fabricated in a dielecmcally isolated complementary bipolar process, occupies a die area of 2mm x 3mm, and consumes 150 mW operating from a
A novel, dual conversion architecture for the Digital Audio Broadcasting (DAB) dual band receiver is introduced. It avoids preselection filters and mini. mizes the number of PLLs by first converting both Lband and Band m inputs to a common 919 MHz intermediate frequency (IF) signal which is then downconverted to the 30 MHz ADC input A carefuily staged gain control strategy is used to meet the challenging sensitivity and intermodulation requirements.Introduction.
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