Careful partitioning of signal. processing tasks between the analog and digital domains to expolit the strengths of each results in an efficient design of a 2lH Q ISDN basic·rate U·interface sin!!;le· chip transceiver. Tbis 5V CMOS device provides transmission across the digital subscriber line at 160kb/s full· duplex, in full compliance with the ANSI standard TL60LAs shown in Figurc 1, the serial 2B+D data from the digital interface is rate.adapted to 160kb/s, and CRC, maintenance, and control bits are inserted in the digital interface section of the cir· cuit (DIF). The resulting data stream is then scrambled and 18bit synchronization words are inserted. Conversion to an 80kHz 4-level signal takes place in the line encoder.The transmitter, shown in Figure 2, includes a 2B1 Q pulsc shaper, a 5-leveI fully-differential PDM D/A converter, a 3rd order transmit filter and a fully-differential line driver. A raised· cosine 780/0 time-roll. off pulse is stored in the pulse shaper, using a PDM code, at 96 samples per baud. Pulse symmetry allows storage of the first half-pulse only. The back-half is generated by a time-mirror circuit. At every baud interval, the current di-bit encodes the pulse front-half, while the past di-bit encodes the pulse back-half. The two resulting quantities are then combined and provided to a 7.68MHz 5-level PDM D I A converter. Un desirable high-frequency components are eliminated by one pole of low·pass filtering in the D/A converter circuit, and two extra poles in the line driver circuit. The time-domain approach used in the transmitter provides a high linearity of the transmitted pulses and eliminates dependence on transformer inductance to meet the ANSI standard template.On the receive side, a hybrid balance circuit substracts a replica of the transmitted signal from the prefiltered receive-line signal; the resuiting signal is band·limited by a 4th.order low-pass Bessel switched-capacitor filter with a cut-off frequency of 40kHz, and amplitude adjusted for maximum range by the AGC block. A 13-bit AID converter samples the analog signal every 12.5I's. A scnsitive 10kHz detector connected in parallel with the prefilter monitors the incoming wake-up tones when the transmitter is inactive. Prefilter, hybrid balance, receive filter, AGC and AID converter have been designed using fully-differ. ential circuit techniques, to increase dynamic range as wcll as power supply rejection and to reduce charge.injeetion related offset. Figure 3 shows the hybrid balance implementation in detail.It is built as a second-order switched-capacitor filter sampled at 960kHz with 32 steps of adaptive gain. Measurements show a linearity of 70dB for a 40kHz sine-wave input signal with a 4.5V peak-to-peak amplitude. The hybrid balance acts as a non-linear echo-canceller, attenuates jitter-induced echo, and improves AID input· signal dynamic range.The AID converter provides 13·bit accuracy, with an inte gral linearity error of ± 1LSB and a differential linearity error of � 0.5LSB. Design aspects of this AID converter...
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