In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.Index Terms-Integrated circuits design, MOSFETs, semiconductor device modeling, variation aware timing. 0018-9383
Capture and emis'-ion processes during charge pumping cn a p-type sub«t ''a i_e v PREFACE This work was conducted as a part of the Semiconductor Technology Program at the National Bureau of Standards (NBS).This program serves to focus NBS research to enhance the performance, interchangeability, and reliability of discrete semiconductor devices and integrated circuits through improvements in measurement technology for use in specifying materials and devices in national and international commerce and for use by industry in controlling device fabrication processes.This research leads to carefully evaluated and well-documented test procedures and associated technology. Special emphasis is placed on the dissemination of the results of the research to the electronics community. Application of these results by industry will contribute to higher yields, lower cost, and higher reliability of semiconductor devices.Improved measurement technology also leads to greater economy in government procurement by providing a common basis for the purchase specifications of government agencies and, in addition, provides a basis for controlled improvements in fabrication processes and in essential device characteristics .The segment of the Semiconductor Technology Program described in this report was supported by The Charles Stark Draper Laboratory, Inc. (CSDL) under CSDL Prime Contract N00030-81 -C-01 33 issued by the Department of the Navy, Strategic Systems Project Office. CSDL's purchase Order Number DL-H-2081 37 covered work at NBS for the period December 1, 1982 through November 30, 1983. Work was monitored by Mr. Robert E. Var of CSDL. The NBS contacts for technical information on this project are Gary P. Carver and Richard A. Wachnik of the Semiconductor Materials and Processes Division at the National Bureau of Standards, (301) 921-3786.
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