The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.
This paper presents a comparative study of six active pixel sensor (APS) schemes by means of simulations and experiments. The optical sensor used was a silicon photodiode with integrated electronics in a standard 0.35 µm CMOS technology. We analyzed how the transistor characteristics, such as channel resistance and leakage current, among others, can influence the APS response. Furthermore, we demonstrated how the choice of APS model affects sensor parameters such as output swing and fill factor, among others. The results presented and the understanding of the operational cycle of the CMOS transfer-gated APS aims at guiding better choices for different applications and the better transistor type in the project.
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