In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10−9 A/cm2 and the smallest interfacial density of states (Dit) of 2.38 × 1012 cm−2 eV−1 have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10−9 A/cm2. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.
In this work, the effects of the atomic-layer deposition
(ALD)-derived
Al2O3 passivation layer with different growth
cycles on the interfacial chemistry and electrical performance of
sputtering-driven ErSmO/InP metal oxide semiconductor (MOS) capacitors
have been comparatively investigated. Atomic force microscopy (AFM)
and X-ray photoelectron spectroscopy (XPS) characterization have confirmed
that the ALD-driven Al2O3 passivation layer
with 20 growth cycles could form a flat dielectric layer and effectively
suppress the diffusion of In and P elements at the InP interface.
Meanwhile, the ErSmO/Al2O3/InP gate stack with
20 growth cycles exhibited optimal electrical properties, including
a large dielectric constant of 37.42, a minimum interface state density
(D
it) of 5.43 × 1011 eV–1 cm–2, and a low leakage current
of 3.95 × 10–6 A/cm–2. The
leakage current conduction mechanisms of InP-MOS capacitors measured
at room temperature and low temperature have also been systematically
analyzed. Particularly, low-frequency noise (LFN) is used to evaluate
trap levels in InP-MOS capacitors. All experimental results have demonstrated
that the ErSmO/Al2O3/InP gate stack has potential
applications in future ultrahigh-speed and high-frequency microelectronic
devices.
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