The design of Digital filters plays a prominent role in the present scenario. The delay and area are the two major components that need to be concentrated on. The delay tap present in FIR filters should be suppressed to inflate the speed of the system. In this paper, the FIR filter design using systolic architecture with associative technique is implemented. This system includes a number of identical elements that are interconnected one after another by programmed manner to get the specified output. Here the proposed systolic FIR is compared with TDA logic block using bisection technique. There will be a greater reduce of critical path using the systolic architecture. To intensify the speed and to truncate the system delay the processing elements such as adders, multipliers and delay elements are designed by reversible logic operations. The proposed filter is better in many aspects such as density of gates, power consumption and delay outputs compared with existing filter. Experimental results are performed using the Xilinx ISE tool.
Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.
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