X ray diffraction, thermogravimetric analysis, scanning electron microscopy and energy disper sive spectroscopy studies were performed with molding sand and sugar industry fly ash to evaluate and com pare their physical properties. We noted that several physical properties of sugar industry fly ash and molding sand were similar. We then tested the permeability, green compression strength and dry compression strength of various compositions of sugar industry fly ash and bentonite to explore their potential as an alternative to molding sand, thereby reducing the dependency on the latter, as well as to suggest an effective way for disposal of fly ash from sugar industry. We also found that quality aluminium castings could be produced using fly ash, which effectively replaced 24% of molding sand in the foundry, thereby reducing the cost of production and increasing the surface finish of castings.
In Digital Image Processing, Median Filter is used to reduce the noise in an image. The med ian filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the p ixels. Sorting in turn consists of comparator which includes adders and mult iplier. Multip lication is a fundamental operation in arith metic co mputing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the mu ltip lier circuits. The Carry Save Array (CSA) mu ltip lier is designed by using the proposed adder cell based on mult iplexing logic. The proposed adder circu it is designed by using Shannon theorem.The mu ltiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based mu ltip lier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based mu ltiplier circu its are simulated by using 90n m feature size and with various supply voltages. The Shannon full adder circu it based mu ltip lier circu its gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.
Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.
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