Due to advancements in device scaling in very-large-scale integration (VLSI) technology, signal integrity (SI) issues play a major role to determining the performance of on-chip interconnects in high-speed digital circuits. The main SI issues are delays, peak voltage noise effects, crosstalk, and timing uncertainties. Here, the SI issues of the coupled multi-walled carbon nanotube (MWCNT) on-chip interconnects are evaluated with and without the effect of shielding technique and compared to the copper interconnects. The MWCNT exhibits an average of 47.9% smaller propagation delays than Cu in dynamic crosstalk conditions. Further, for crosstalk reduction, the active shielding (AS) and passive shielding (PS) techniques are proposed. With the AS and PS techniques, the MWCNT interconnects experience a decreased delay by 46.8% and 30.15% compared to without shielding technique, respectively. Moreover, the AS exhibits smaller crosstalk effects than the PS technique due to its input switching activities on shielded lines. In addition, the quality of the signal (QoS) and Intersymbol interference (ISI) noise effects of coupled MWCNT interconnect with and without shielding is evaluated. Finally, to improve the QoS and reduce the ISI effects, the decision feedback equalizer with the least mean square adaptive algorithm is implemented at the receiver end.
There is a huge exponential growth in the area occupied by the embedded memories on the System-on-Chip (SoC) because of the data that the users prefer to store in the devices. The expectation of the user is that it has to be very precise and accurate at the same time. Hence there is a need for testing these modules once in a while for which Built in Self Test was introduced in recent years. Testing is only an initial part after which comes the repairing where the faults detected during testing must be answered. In this paper March SS algorithm is implemented to test an embedded memory in such a way that the steps in the algorithm is converted into microcode that is the most optimized way of implementing a algorithm that is used for testing in BIST module. Along with BIST an enhancement where we can repair the faulty address locations is included which does the repairing by the means of a Redundancy module. Due to this we can have the best implementation where we can have a testing as well as repairing the faulty address location in a single SoC. The proposed architecture was implemented using Verilog HDL, simulated using Xilinx simulation tool and synthesis by Xilinx Synthesis tool.
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