In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than ±0.4 μm. Even an offset in an individual UR can cause the degradation. At a low drain bias of −0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to −10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.
Learning should not be hindered by ones' age, gender or capacity of literacy. But very often people's right to learn is limited exactly due to these reasons. This paper shows how a group of older people, organized by a community leader to form a learning group, used multiple approaches in order to overcome the obstacles that block people, especially women, from learning. The learning group lasted for more than four years, and they were invited to attend the commencement of a nearby university.
This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.
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