Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.
In this paper we will investigate techniques to minimize the energy consumed by a secure wireless session without compromising the security of the session. While it has been shown in [8] that compressing the session negotiation messages, the protocol header, and the data reduces the energy consumed by a secure session [8], in this paper we show that matching the block size of compression to the data cache size of the device is important. We also investigate the choice of a bulk encryption algorithm (3DES vs. AES) and a key exchange protocol (DiffieHellman vs. RSA) based on the energy consumed by a secure wireless session. These techniques yield energy savings of 1.3x during data transmission and 1.2x during data reception beyond those obtained by techniques in [8]. These techniques complement and supplement those proposed in [8], and when combined, yield an overall energy savings of 2.1× during data transmission and 4.35× during data reception.
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