No abstract

No abstract

No abstract

Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength regime. The poly gate distortion affects electrical characteristics of a device, including drive current (I on ), leakage current (I off ), and threshold voltage (V t ). For circuits such as compact memory cells which are sensitive to geometry variations, electrical performances can vary with the image distortion of each transistor even with resolution enhancement technologies (RETs) such as optical proximity corrections. In this paper, we demonstrate the impacts of OPC settings on the performance of a 6T-SRAM cell. The printed gate-region and active-region patterns are simulated by an in-house OPC engine we developed. A device model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of smaller rectangles. Consequently, electrical performance such as static noise margin (SNM) can be obtained by incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as segmentation length and number of corrections can affect wafer image quality and electrical performance in different ways.

Electron-beam–direct-write lithography at lower accelerating voltages has been considered as a candidate for next-generation lithography. Although long-range proximity effects are substantially reduced with the voltage, proximity effect correction (PEC) is still necessary since short-range proximity effects are relatively prominent. The effectiveness of model-based PEC can be limited severely if an inaccurate point spread function (PSF) characterizing electron scattering within resist is adopted. Recently, a new PSF form using a promising calibration method has been developed to more accurately characterize the electron scattering and thus significantly improve patterning fidelity at 5 keV. However, influences of adopting the conventional and new PSF forms for the usage of patterning practical circuit layouts have not been intensively studied. This work extensively investigates impacts of PSF accuracy on patterning prediction and PEC under different resist thickness conditions suitable for various lithographic half-pitch nodes, where the critical features of practical circuit layouts are used to quantitatively evaluate their performance. In addition, patterning fidelity limitation suffered from proximity effects is examined to determine whether PEC should be applied. Simulation results indicate that the new PSF form can significantly improve the fitting accuracy, patterning prediction, and PEC results over the conventional PSF forms, especially for circuit layouts with smaller feature sizes.