Smart devices are omnipresent today and the design of these embedded systems requires a multidisciplinary approach. It is important that students in electrical engineering and computer science learn these different aspects of embedded systems design. Our course on Complex Systems Design Methodology presents an overview of embedded systems design with a strong focus on the main concepts, preparing the students for more detailed follow-up courses on specific topics. Imparting the theoretical concepts to the students is not sufficient, however. Hands-on sessions are indispensable for the students to acquire the necessary skills. In this article we present our approach for these hands-on sessions, which is to pose relatively small problems in separate sessions, each focusing on a single design aspect. Five years after the introduction of this new course at Ghent University, we can conclude that students not only like this course, but that their design skills have also improved by our new, aspectfocused, approach
Dynamic hardware generation is a powerful technique that can substantially reduce both the required hardware resources and the time needed to perform a calculation, reflected in an improved functional density. This performance improvement is a result of additional run-time optimizations enabled by the knowledge of values at certain inputs at runtime. However, due to the large overhead conventional hardware generation tools incur, the usability of dynamic hardware generation is limited. We present a dual approach that combines compile-time generation of generic hardware and run-time specialization. This drastically decreases the dynamic generation overhead. Our approach is used for dynamic generation of FIR filters and compared to a static and a conventional dynamic implementation. The experiments clearly show that the dual approach improves the usability of dynamic hardware generation.
The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conventional sequential programming paradigm for parallel programming: single-threaded designs must be decomposed into dependent, interacting tasks. The Java programming language has built-in thread support and is therefore suitable for the development of parallel software. We are working on a framework and tool support to assist the programmer with the tedious task of parallel programming.
Application-specific hardware accelerators can significantly improve a system's performance. In a Java-based system, we then have to consider a hybrid architecture that consists of a Java Virtual Machine running on a general-purpose processor connected to the hardware accelerator. In such a hybrid architecture, data communication between the accelerator and the general-purpose processor can incur a significant cost, which may even annihilate the original performance improvement of adding the accelerator. A careful layout of the data in the memory structure is therefore of major importance to maintain the acceleration performance benefits.This article addresses the reduction of the communication cost in a distributed shared memory consisting of the main memory of the processor and the accelerator's local memory, which are unified in the Java heap. Since memory access times are highly nonuniform, a suitable allocation of objects in either main memory or the accelerator's local memory can significantly reduce the communication cost. We propose several techniques for finding the optimal location for each Java object's data, either statically through profiling or dynamically at runtime. We show how we can reduce communication cost by up to 86% for the SPECjvm and DaCapo benchmarks. We also show that the best strategy is application dependent and also depends on the relative cost of remote versus local accesses. For a relative cost higher than 10, a self-learning dynamic approach often results in the best performance.
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