AbstiactIncreases in delay due to coupling can have a dramatic impact on IC pe~ormance for deep submicron technologies. To achieve marimum pe~ormance there is a needfor analyziltg logic stages with large complex coupled interconnects. In timirtg analysis, the worst-case delay of gates along a critical path must include the eflect of noise due to switching of nearby aggressor gates. In this papec we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align agsressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transtitor-level and celllevel. IIt addition, we prove that the waveforms generated in our methodology converge under typical timing a~lysis conditions.
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