In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-in diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency > 98% while maintaining a wide doping window of up to ∼ 5×10 17 cm −3 at a minimum reverse blocking efficiency of ∼ 90% extending well into high 10 17 cm −3 range (∼ 8×10 17 cm −3). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.

While a slew of edge termination schemes for gallium nitride (GaN) power devices have been proposed and experimentally demonstrated to date, all of them suffer from the inability to achieve breakdown voltage close to ideal parallel-plane breakdown voltage. Further, they are exclusively processed using implantation or dry etching based methods, both of which are known to introduce additional defects and lattice damage leading to large leakage components. In this work, we develop and design novel dielectric vertical sidewall appended edge termination (DiVSET) schemes that are surface-charge resilient and capable of achieving ideal parallel-plane breakdown voltage. These edge termination schemes are compatible with plasma-assisted molecular-beam epitaxy facilitated silicon nitride shadowed selective-area growth (SNS-SAG) processing protocol, recently developed by us. The SNS-SAG protocol is uniquely capable of processing smooth, lattice damage-free GaN interfaces and vertical sidewalls that can reduce the leakage current by several orders of magnitude compared to conventional implant and dry etching based GaN processing. Together with the SNS-SAG processing, the DiVSET schemes offer an enabling technology for high-performance ultra-low leakage GaN power devices.

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In this paper, we describe the development of moving mesh adaptation framework, and its application to charge transport simulation of semiconductor devices, with emphasis on its relevance to power semiconductor devices. Mesh adaptivity in the context of semiconductor device simulation is an important problem and can help deal with the convergence and numerical stability issues, as well as automate the meshing process. We demonstrate the efficacy of our proposed meshing scheme through the simulation of a GaN based power diode, as well as a Si diode with a non-rectangular doping profile, by externally coupling our framework to Sentaurus Device TCAD. We perform error analysis and compare our results with simulations based on high-resolution uniform structured meshes as well as manually refined axis-aligned meshes. In addition to the benefits in terms of accuracy, automation, and generality, our method can be regarded as a stepping stone towards computationally scalable and adaptive semiconductor device simulations.

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Modern high-speed power applications require diodes with high-current capacity, larger reverse blocking voltage, lower reverse recovery transients, and lower leakage. GaN mixed-conduction vertical diodes are an attractive option for these operations. Experimentally reported GaN diodes have two major shortcomings, namely, higher leakage due to non-optimum design and conventional processing methods (e.g. ion implantation and dry etching), introducing huge leakage components. In this work, we design ultra-low leakage GaN buried p-base merged p-i-n Schottky and buried p-base merged p-i-n junction barrier controlled Schottky diodes, capable of reducing leakage current by more than five orders of magnitude by virtue of strong reduced surface field effect. Moreover, these designs are fully compliant with our earlier reported silicon nitride shadowed selective-area growth (SNS-SAG) methodology, capable of reducing the leakage by at least four orders of magnitude. In combination with SNS-SAG and highly efficient dielectric vertical sidewall edge termination scheme, these designs provide attractive options for higher performance.

Successful development of Broadband over Power Lines (BPL) is obviously a potential solution for wireless communication systems with the existing infrastructure. Multi-Carrier Code Division Multiple Access (MC-CDMA) with Orthogonal Frequency Division Multiplexing (OFDM) modulation technique is a promising solution for a frequency selective fading with impulsive noises of the PLC channel. A linear iterative receiver with a Finite State Markov Channel (FSMC) model is proposed to remove Multiple Access Interference (MAI) and Inter Symbol Interferences (ISI). In this paper we focused on Maximum Likelihood (ML) feedback detection by introducing FSMC to get significant improvement in Bit Error Rate (BER). This model of the receiver is more robust against Gaussian colored and impulsive noises of the PLC channel.

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