We propose a parallel router architecture for processing networLlayer protocob at FDDI (Fiber Distributed Data Interface) speeds. A t high speeds the computing power of the ezwtang routers becomes the performance bottleneck (for processing small frame razes). Hence a completely diflerent approach is required in designing a router. The opportunities of parallel processing in a network protocol are investigated in thid paper. Several levels of parallel processing are considered and an architecture for the most practical and femible approach w proposed. The concept of a snoopy header cache w introduced. Algorithm for reducing the mean processing delay by balancing the load among the processors are dhcwsed. The performance of the router is evaluated by analytic methods and is compared with simulation results. The results from both the analytic model and the simulator reinforce the choice of a header cache in a multiprocessor environment.
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