This paper provides a review of both Rent's rule and the placement models derived from it. It is proposed that the power-law form of Rent's rule, which predicts the number of terminals required by a group of gates for communication with the rest of the circuit, is a consequence of a statistically homogeneous circuit topology and gate placement. The term "homogeneous" is used to imply that quantities such as the average wire length per gate and the average number of terminals per gate are independent of the position within the circuit. Rent's rule is used to derive a variety of net length distribution models and the approach adopted in this paper is to factor the distribution function into the product of an occupancy probability distribution and a function which represents the number of valid net placement sites. This approach places diverse placement models under a common framework and allows the errors introduced by the modeling process to be isolated and evaluated. Models for both planar and hierarchical gate placement are presented.

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog block s. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control.We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

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A first-order differential equation for placement analysis is derived by considering the competing processes that generate and terminate wires crossing a circuit partition. The solution of this equation provides an estimate for the number of wires needed by a circuit partition for external communication and corresponds to the information normally associated with Rent's rule. The rate model is shown to account not only for the simple power-law form of Rent's rule for small partition sizes but also for deviations from power-law behavior observed for larger partition sizes. The accuracy of the model is validated by comparing solutions of the differential equation with experimental data extracted from a variety of netlists. The netlists, ranging from 10 000 to 68 000 cells, were optimized using a commercial placement tool. The accurate modeling of terminal-cell data results in a more robust predictive model for the distribution of wire lengths. This improved model accurately captures the change in the distribution of wires as the level of circuit placement optimization ranges from random to highly optimized placement. In addition, the new model provides an explanation for the experimentally observed inflection point and local maximum in the wire length distribution of some netlists.