Molecular beam epitaxy was employed for the growth of HgCdTe-based n-p + -n device structures on (211)B oriented CdZnTe substrates. The device structures were processed as mesa isolated diodes, and operated as back-to-back diodes for the simultaneous detection of two closely spaced sub-bands in the mid-wave infrared spectrum. The devices were characterized by R 0 A values in excess of 5 × 10 5 Ω cm 2 at 78K, at f/2 fov and quantum efficiencies greater than 70% in each band. Infrared imagery from a focal plane array with 128 × 128 pixels was acquired simultaneously from each band at temperatures between 77 to 180K, with no observable degradation in the image quality with increase in temperature.

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Chemical doping of HgCdTe is an important issue in II–VI compound semiconductors. In this paper, we will report on the molecular-beam epitaxy (MBE) growth and characterization of n- and p-type HgCdTe. We have grown n- and p-type layers of HgCdTe with indium and arsenic as the dopants using MBE at 170 °C–180° C without photo or ion excitation. The doped layers, which range from 1015 cm−3 to 1018 cm−3 have been characterized by a variety of techniques including infrared IR transmission, Hall measurement, scanning electron microscopy, minority carrier lifetime, and secondary ion mass spectroscopy. The results indicate that n-type alloy layers are easier to form than p type because of the efficient incorporation of indium in the mercury (or cadmium) sublattice. Memory effects of indium were not observed. We have also demonstrated that our p-type layers remain p type after mercury anneal indicating that they are extrinsically doped. The breakthrough in chemical doping of HgCdTe has enabled us to grow several double layer heterojunction structures. Several diodes have been fabricated and their electrical and optical characteristics are discussed.

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MOC-VPE using TMG and AsCI:~ for the GaAs:~ growth shows promising features. It excludes the liquid source instability and fatally toxic AsH:~. At III/V ratios less than 2.3, the wall deposition in the mixing region was suppressed and GaAs layers with smooth surface were grown. In this III/V ratio range the growth rate increased as the TMG flow rate increased and the AsCI~ flow rate decreased. The growth rate could be controlled over a wide range between 300 and 4000 ~/min. The growth rate is independent of the mixing temperature, which means that MOC-VPE is a singte-temperature method like MOVPE. The substrate was gas etched with a smooth surface at low III/V ratios. Though carbon may have been introduced into the epitaxial layer, a high purity GaAs epitaxial layer with a 77 K mobility of 36,000 cm2/V and a 77 K electron concentration of 1.4 • 10 TM cm -3 was obtained.It should be noticed that a widely used chloride VPE system can be used for MOC-VPE with only a slight SCIENCE AND TECHNOLOGY April 1985 modification of the reactor inlet. Furthermore, the in situ gas etching necessary for a well-controlled interface between the substrate and the epitaxial layer can be easily carried out in the MOC-VPE system by reducing the III/V ratio. ABSTRACTThe chemical state and concentration of phosphorus in SiO2 influence its thermal flow and etch rate. These properties of phosphorus-doped SiO2 are quite important in both bipolar and MOS VLSI, and they influence the final yield of these circuits. In this paper, ESCA and Auger measurements were made to determine the chemical state of phosphorus in SiO~ and its distribution through the film. Samples studied were CVD SiO2 containing 8% phosphorus by weight, and ion-implanted phosphorus in thermal SiO2, both annealed and unannealed. ESCA data confirmed the existence of two types of states corresponding to P-O bonds and P-Si bonds. The change in these states due to annealing is discussed. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 157.182.150.22ABSTRACT Submicron silicon epitaxial films have been deposited at low temperatures using only wet chemical cleans for the substrate surface preparation. The layers have been assessed by crystallographic (RHEED) techniques coupled with the electrical measurement of Schottky barrier diodes and transistors fabricated in the layers. In addition, XPS studies of the substrate surface prior to the deposition are also reported. Good quality epitaxial films have been produced at deposition temperatures of 900~ and below.