chip data memory which is mapped into a part of We present a new cache memory system to the linear address space of the off-chip main reduce cache miss ratio. It enables cache to lock or memory. It is accessible by means of the same way release the data in it by software controls. This as main memory. The difference between the paper describes its overview hardware and scratch-pad memory and data cache is that the programming directions. And we show the scratch-pad guarantees a single-cycle access time, performance evaluations. The results show that whereas the data cache can not do because of the computer with this system can reduce the cache misses. I n multi-programming environment, cache misses up to 60.9% and execute faster than the scratch-pad degrades the performance the computer with a conventional cache.because all data in the scratch-pad must be
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