Quantum computers for the efficient simulation of physical systems are emerging today. Effect of Spin on Quantum Dots (QDs) paved the way for QCA. Quantum-dot cellular automata (QCA) have a simple cell as the basic element. The cell is used as a building block to construct gates and wires.Reversible logic has extensive applications in quantum Computing. Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Reversible gates such as Fredkin and DKG gates can be of great use for the implementation of the logic designs. Recent advances in reversible logic allow for improved quantum computer algorithms and schemes for corresponding computer architectures.In this paper, a design constructing the hybrid adder -Subtractor based on reversible logic gates as logic components using QCA is proposed. By using reversible logic gates instead of using traditional logic gates such as AND, OR, XOR, NOT, a Hybrid reversible Adder -Subtractor whose function is the same as the traditional Adder and Subtractor are designed and compared with the functioning of DKG gate based adder-subtractor. The simulation results shows that higher speed, smaller size and lower power consumption can be achieved with the proposed HAS system.
GeneralTermDesign
Error detection is the detection of errors caused by noise or other impairments during the transmission of signal from transmitter to receiver. Logic design errors may occur during simulation and synthesis due to increase in the complexity of CMOS and VLSI circuits. Error detection method can be either systematic or non-systematic. In systematic method, the transmitter sends the original data unit, and a fixed number of check bits or Parity data is been attached to it, which are derived from the same input data unit. In this work, we describe a method of error detection in 4-bit multiplier with parity predictor circuit in QCA tool. 4-bit multiplier is used as a logic in which we detect error according to its input data. The outputs of logic used and the parity predictor are then compared using comparator. If the values do not match, error has occurred. The technique we used is Concurrent error detection using parity predictor circuit.
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