Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks which works well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a High Speed & low area architecture for the shift and add multiplier is proposed. The simulation result for 8 bit multipliers & four tap Filters shows that the proposed Low Area & Delay architecture lowers the total Area & Delay when compared to the Array Multiplier and Booth Multiplier architecture based Filter. To develop the system blocks in Modelsim 6.4a and Xilinx ISE9.1i, the Spartan3 FPGA tool is used which achieves the simulation and the synthesis of the proposed multiplier. Verilog HDL is the language used for designing the proposed multiplier.
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