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We present measurements of the capacitive coupling energy and the inter-dot capacitances in a linear quadruple quantum dot array in undoped Si/SiGe. With the device tuned to a regime of strong (>1 GHz) intra-double dot tunnel coupling, as is typical for double dot qubits, we measure a capacitive coupling energy of 20.9 ± 0.3 GHz. In this regime, we demonstrate a fitting procedure to extract all the parameters in the 4D Hamiltonian for two capacitively coupled charge qubits from a 2D slice through the quadruple dot charge stability diagram. We also investigate the tunability of the capacitive coupling energy, using inter-dot barrier gate voltages to tune the inter-and intradouble dot capacitances, and change the capacitive coupling energy of the double dots over a range of 15-32 GHz. We provide a model for the capacitive coupling energy based on the electrostatics of a network of charge nodes joined by capacitors, which shows how the coupling energy should depend on inter-double dot and intra-double dot capacitances in the network, and find that the expected trends agree well with the measurements of coupling energy.

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Fast operations, an easily tunable Hamiltonian, and a straightforward two-qubit interaction make charge qubits a useful tool for benchmarking device performance and exploring two-qubit dynamics. Here, we tune a linear chain of four Si/SiGe quantum dots to host two double dot charge qubits. Using the capacitance between the double dots to mediate a strong two-qubit interaction, we simultaneously drive coherent transitions to generate correlations between the qubits. We then sequentially pulse the qubits to drive one qubit conditionally on the state of the other. We find that a conditional π-rotation can be driven in just 74 ps with a modest fidelity demonstrating the possibility of two-qubit operations with a 13.5 GHz clockspeed.

We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.