This paper presents the single-event upset characterization of a commercial field programmable gate array (FPGA) using electron radiation. FPGA radiation test results under high energy electrons are described and the dependence between electron energy and SEU cross section is highlighted. A technological cross section is performed to evaluate the back end of line (BEOL) layers composition and thickness. These values are used to perform Monte Carlo simulations of the commercial FPGA exposed to 20-MeV primary electron beam. Calculation results show that electrons are able to generate SEU on the FPGA embedded RAM and confirmed experimental data. SEU rates induced by Jovian electrons are estimated using two different tools: Monte Carlo in GEANT4 and the OMERE Software.Index Terms-45-nm FPGA, embedded RAM, high-energy electron, Monte Carlo simulation, radiation test, SEU rate, single-event upset.

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With the increase of sensitivity of devices to singleevent upsets (SEUs), the possibility to trigger an upset with incident electrons has been recently raised. All the mechanisms susceptible to trigger the SEUs are investigated in detail. New measurements performed on the field programmable gate array static random access memory based from Xilinx Spartan 6 at 1 MeV seem to confirm two SEU regions with the transition located around 10 MeV.

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