Diabetic retinopathy (DR) is a human eye disease that affects people who are suffering from diabetes. It causes damage to their eyes, including vision loss. It is treatable; however, it takes a long time to diagnose and may require many eye exams. Early detection of DR may prevent or delay the vision loss. Therefore, a robust, automatic and computer-based diagnosis of DR is essential. Currently, deep neural networks are being utilized in numerous medical areas to diagnose various diseases. Consequently, deep transfer learning is utilized in this article. We employ five convolutional-neural-network-based designs (AlexNet, GoogleNet, Inception V4, Inception ResNet V2 and ResNeXt-50). A collection of DR pictures is created. Subsequently, the created collections are labeled with an appropriate treatment approach. This automates the diagnosis and assists patients through subsequent therapies. Furthermore, in order to identify the severity of DR retina pictures, we use our own dataset to train deep convolutional neural networks (CNNs). Experimental results reveal that the pre-trained model Se-ResNeXt-50 obtains the best classification accuracy of 97.53% for our dataset out of all pre-trained models. Moreover, we perform five different experiments on each CNN architecture. As a result, a minimum accuracy of 84.01% is achieved for a five-degree classification.

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The electrification of vessels/ferries for green transformation requires onboard electrical energy storage as well as an energy supply network in the port area. In this context, a lot of efforts have been made in the last decade that have been reviewed in such a way that only a single aspect of the green transformation challenge is highlighted. Consequently, the objective of this research is to develop knowledge by examining the current state of affairs and provide, accordingly, abstract implementation guidelines for green transformation through vessel/ferry electrification. A comprehensive study on the electrification of vessels, in industry as well as in academia, is performed. Based on the data collected through a systematic study, a comparison of various pure electric and hybrid vessels in terms of certain performance attributes, such as battery capacity, passenger and cargo capacities, and size (length) of the vessel, is performed. Moreover, the distribution of vessels according to different countries and manufacturers is provided. Finally, certain technical, operational, and legislative challenges are explored.

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The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over GF(2m). This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.

The size of neural networks in deep learning techniques is increasing and varies significantly according to the requirements of real-life applications. The increasing network size, along with the scalability requirements, poses significant challenges for a high performance implementation of deep neural networks (DNN). Conventional implementations, such as graphical processing units and application specific integrated circuits, are either less efficient or less flexible. Consequently, this article presents a system-on-chip (SoC) solution for the acceleration of DNN, where an ARM processor controls the overall execution and off-loads computational intensive operations to a hardware accelerator. The system implementation is performed on a SoC development board. Experimental results show that the proposed system achieves a speed-up of 22.3, with a network architecture size of 64X64, in comparison with the native implementation on a dual core cortex ARM-A9 processor. In order to generalize the performance of complete system, a mathematical formula is presented which allows to compute the total execution time for any architecture size. The validation is performed by taking Epileptic Seizure Recognition as the target case study. Finally, the results of the proposed solution are compared with various state-of-the-art solutions in terms of execution time, scalability, and clock frequency.

Engineering studies consist of two parts: theory lectures and laboratory practices. Effectiveness of laboratories plays an important role in providing necessary design skills. However, evaluation of laboratories can be subjective and inconsistent. Consequently, a criterion is required to evaluate the engineering laboratories. This paper proposes an evaluation criterion for assessing the effectiveness of engineering laboratories in terms of pedagogic aspects. The identified pedagogic aspects in this paper are: relationship between theory and laboratory practice, content level, activity level, learning environment and laboratory manual. We evaluated seven different laboratories and generated recommendations based on our evaluation results.

Consumer electronic manufacturing (CEM) companies maintain a range of electronic products that are designed and tested according to the type and end-user requirements. These electronic products go through a validation and verification test for proof of design and a manufacturing test for checking reliability, quality, and manufacturing defects. Testing is carried out using test sites, designed based on the electronic product type. Currently, there is no standard approach for setting up a test site for electronic products. In this research, two processes are presented, for setting up new test sites and optimization of existing test sites for consumer and other electronic products. The proposed processes include a voice of customer (VoC) interface, that is based on a unique dataset and through machine-learning technique automatically translate customer information into customer requirements, and a figure of merit (FoM) presented as an outcome of this research using several key test-related parameters. These proposed processes are an important step towards defining a standard approach for setting test sites for consumer and other electronic products. The processes are implemented using a software application developed in LabVIEW, which is linked to a database containing test data for around 400 products collected as part of this research and form a knowledge base for the proposed processes. Finally, the processes are validated by setting up a new experimental test site for an RF receiver and optimization of an existing test site of an antenna system.INDEX TERMS Consumer electronic manufacturing (CEM), electronic product test, figure-of-merit (FoM), LabVIEW, machine-learning, voice of customer (VoC).