Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(IV)O3)2](4-) as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(v)2O6](2-) moiety containing a {Se(V)-Se(V)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call 'write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

Single-photon detection has emerged as a method of choice for ultra-sensitive measurements of picosecond optical transients. In the short-wave infrared, semiconductor-based single-photon detectors typically exhibit relatively poor performance compared with all-silicon devices operating at shorter wavelengths. Here we show a new generation of planar germanium-on-silicon (Ge-on-Si) single-photon avalanche diode (SPAD) detectors for short-wave infrared operation. This planar geometry has enabled a significant step-change in performance, demonstrating single-photon detection efficiency of 38% at 125 K at a wavelength of 1310 nm, and a fifty-fold improvement in noise equivalent power compared with optimised mesa geometry SPADs. In comparison with InGaAs/InP devices, Ge-on-Si SPADs exhibit considerably reduced afterpulsing effects. These results, utilising the inexpensive Ge-on-Si platform, provide a route towards large arrays of efficient, high data rate Ge-on-Si SPADs for use in eye-safe automotive LIDAR and future quantum technology applications.

The development of nanofabrication techniques for creating high aspect ratio (∼50:1) sub-10 nm silicon nanowires (SiNWs) with smooth, uniform, and straight vertical sidewalls using an inductively coupled plasma (ICP) etching process at 20 °C is reported. In particular, to improve the quality and flexibility of the pattern transfer process for high aspect ratio SiNWs, hydrogen silsesquioxane, a high-resolution, inorganic, negative-tone resist for electron-beam lithography has been used as both the resist for defining sub-10 nm patterns and the hard mask for etching the underneath silicon material. The effects of SF6/C4F8 gas flow rates, chamber pressure, platen power and ICP power on the etch rate, selectivity, and sidewall profile are investigated. To minimize plasma-induced sidewall damage, moderate plasma excitation power (ICP power of 600 W) and low ion energy (platen power of 6–12 W) were used. Using the optimized etch process at room temperature (20 °C), the authors have successfully fabricated sub-10 nm SiNWs, which have smooth vertical sidewall profile and aspect ratios up to ∼50:1. This optimized etch combined with a controlled thermal oxidation allows the realization of consistent, reproducible, and reliable SiNW devices with nominal widths from 100 nm down to sub-5 nm in silicon on top of SiO2 fabricated on silicon on insulator substrates.

Silicon nanowires have been patterned with mean widths down to 4 nm using top-down lithography and dry etching. Performance-limiting scattering processes have been measured directly which provide new insight into the electronic conduction mechanisms within the nanowires. Results demonstrate a transition from 3-dimensional (3D) to 2D and then 1D as the nanowire mean widths are reduced from 12 to 4 nm. The importance of high quality surface passivation is demonstrated by a lack of significant donor deactivation, resulting in neutral impurity scattering ultimately limiting the electronic performance. The results indicate the important parameters requiring optimization when fabricating nanowires with atomic dimensions.

Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.