Multilevel inverters are a new family of converters for dc-ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with a lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology, which consists of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count, exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in this paper to demonstrate the features of the proposed topologies. Several experimental results have been included in this paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes. INDEX TERMS Asymmetric, hybrid inverter, inverter topology, multilevel inverter, MLI, nearest level control, power electronics, single-phase inverter, reduce switch count.

Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output. INDEX TERMS Basic unit, cascaded inverter, multilevel inverter (MLI), selective harmonic elimination, SHEPWM, optimization, reduce switch count. II. ANALYSIS AND DESCRIPTION OF PROPOSED MULTILEVEL TOPOLOGY A. BASIC UNIT OF PROPOSED TOPOLOGY

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This study presents selective harmonic elimination pulse width modulation technique-based hybrid asynchronous PSO-Newton-Raphson (APSO-NR) algorithm for the elimination of undesired harmonics in cascaded H-bridge multilevel inverter. The proposed algorithm is applicable to all levels of MLI having equal and non-equal DC sources. In the proposed method, ring topology-based APSO algorithm is hybrid with NR method. APSO worked as a global search technique and NR is used for the refinement of best solutions. APSO-NR is applied to the seven-level inverter to eliminate fifth and seventh harmonics. In simulations, the performance of the proposed algorithm is compared with genetic algorithm, bee algorithm and particle swarm optimisation. The results proved that the proposed algorithm is efficient, and gives more precise firing angles in less number of iterations with high capability of tackling local optima. For the 48% of modulation index range, APSO-NR minimised the fitness function value lower than (10 −25). The proposed algorithm is validated through the experimental implementation of the three-phase seven-level inverter.

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