The quantum confinement effect (QCE) in ultranarrow silicon nanowire channel field-effect transistors (FETs) as well as single-electron/hole transistors (SET/SHTs) operating at room temperature is intensively investigated for the optimization of device design and fabrication. By adopting a “shared channel” structure with the directions of <110> and <100>, a carrier-dependent QCE is systematically examined. It is found that <110> nanowire pFETs exhibit a smaller threshold voltage (V th) variability due to a weaker QCE, while <110> nFETs and <100> n/pFETs show comparable V th variabilities coming from the QCE. It is also found that only SETs exhibit clear Coulomb oscillations in the case of the <110> channel, suggesting the formation of higher tunnel barriers than SHTs. On the other hand, <100> SHTs show undesirable multidot behavior in spite of their comparable QCEs for electrons and holes. It is concluded that <110>-directed nanowire channel SETs and n/pFETs are suitable for the integration of CMOS and SETs.

Silicon-based single-electron transistors (SETs) and complementary metal–oxide–semiconductor (CMOS) devices have been integrated onto a single chip, and the operation of SET/CMOS integrated circuits has been demonstrated at room temperature. The fabrication process of SETs has been improved in terms of parasitic resistance suppression, threshold voltage control, and reduction in required time for electron-beam lithography for integration with CMOS devices. There is no significant degradation in the characteristics of CMOS devices owing to the special fabrication process of SETs operating at room temperature. CMOS 1-bit analog selectors, which are building blocks of multibit address decoders, have been combined with SETs, and the circuit operation has been demonstrated at room temperature for the first time. These results show the feasibility of SET/CMOS integrated circuits composed of high-density arrays of SETs and high-performance CMOS peripheral circuits, which fully leverage the advantages of SETs and CMOS.

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A single electron transistor (SET) with floating gate, which has a non-volatile memory effect, is successfully integrated with MOS circuits. By applying high voltage generated by the charge pump circuit to the floating gate SET, the characteristics control of Coulomb blockade oscillation is demonstrated for the first time at room temperature. This attempt will open a new path of adding new functionality to conventional MOS circuits by integration with so-called Beyond CMOS devices.