With the modernization of Department of Defense (DoD) systems and the growing complexity of communication equipment, traditional test methods and processes have to evolve in order to maintain their effectiveness. DoD acquisition policy requires the use of modeling and simulation (M&S) in all phases of system development life-cycles in order to ensure technical certification and mission effectiveness. The complexity of these systems poses significant challenges over traditional interoperability test methodologies. The Automated Test Case Generator (ATC-Gen), funded by the Joint Interoperability Test Command (JITC), captures a Military Standard (MIL-STD) 6016C document and translates it into rules. These are in turn formalized into test cases using the Discrete Event System Specification (DEVS). In this paper, we present a new methodology to generate the test models and perform conformance testing using system theory, the DEVS M&S framework, the System Entity Structure (SES), and Extensible Markup Language (XML). This new methodology promotes the separation of the models, the simulator, and the distributed simulation. These separations distinguish and promote reusability by developing models, the simulator, and distributed simulation independently. The DEVS test models are generated from the test cases by the Test Model Generator using the system specifications. These models are written in an XML-SES format; the resulting C++ DEVS source code is generated based on the test model XML file. The Test Driver (TD) was designed based on the Model/Simulator/View/Control (MSVC) design pattern and developed to execute the DEVS test models. MSVC supports model and simulator separation design. It was also designed to support multiple network simulation protocols and rapid software modifications in order to incorporate new network protocols into the simulation software. This methodology was used to verify the conformance of the Integrated Architecture Behavior Model (IABM) to the MIL-STD 6016C, and the results of the test scenarios were validated using the JITC's Simple J network packet-monitoring tool. The network packet monitor captured the transmissions and the receipt of the tactical data messages from the TD. The system analyst interpreted and verified the messages, and determined whether these messages were the intended behavior of the TD.
This paper introduces a method of achieving the finite-state global behavior of a reconfigurable automation system that consists of sub-components and which can be another component in a higher-level system. The approach introduced here is based on the discrete event system specification (DEVS) that has been regarded as a powerful simulation tool for modular and hierarchical systems, but its global states for whole behavior can be infinite.To achieve the finite state behavior that is needed for quantitative and qualitative analysises of a system, this paper introduces a new class of DEVS, called schedule-controllable DEVS (SC-DEVS) that can be seen as a middle class between the ordinary DEVS and schedule-preserved DEVS (SP-DEVS) that was proven that the global behavior of SP-DEVS networks can be abstractedin a finite number of states. The condition for finite-state space of SC-DEVS networks is addressed in the paper. In addition, the comparison between SC-DEVS and SP-DEVS in terms of the number of states and the time consumed in the generation procedure is illustrated by using a cluster tool example.
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