Reconfiguration for fault tolerance is a widely studied field, but this work applies graph grammars to this discipline for the first time. Reconfiguration Graph Grammars (RGG) are defined and applied to the definition of processor array reconfiguration algorithms. The nodes of a graph are associated with the processors of a processor array, and the edges are associated with those interprocessor communication lines that are active. The resulting algorithms for dynamic (run-time) reconfiguration are efficient and can be implemented distributively.
Keal-time digital signal processing jor critical applications demands that rapid, .succes@l reconflguration techniques he employed to increase fault tolerance. To meet this need, we introduce and dunonstrate a IocaI area reconjiguration algorithm, fbr a rectangular processor arra,v that is very eflcient, does not require a host processor, and will successfully recot&ure jor a fault anywhere in the locnl area rfthere is an available spare. Further, ifall the spares in a local area are used, areas can he conihined in a .svj%vare c:ontrolled procr.cv, preventing a .systemfiJilure.
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