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The conventional hardware/software codesign cannot meet the requirement for a PSO algorithm that needs to be changed for different applications. In addition, the architecture of the conventional hardware/software codesign leads to a low processing speed. This paper presents a flexible hardware/software codesign to support various PSO algorithms and increase the processing speed of the conventional hardware/software codesign for various PSO applications. By adopting a simplified hardware architecture, the calculation speed can be improved by reducing the communication overhead. Furthermore, an improved generic particle calculation block (GPCB) is used to enhance the flexibility. It selects an appropriate PSO algorithm without the need for hardware modification to further increase the processing speed. The experimental results proved that the proposed flexible hardware/software codesign can achieve high processing speed and high flexibility with low chip cost.

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for calculating various complex mathematical functions and has been widely used to accelerate embedded processors. The conventional CORDIC hardware cannot achieve high flexibility and high calculation precision simultaneously. This paper presents a programmable architecture of the CORDIC algorithm to calculate various complex mathematical functions with high flexibility, high calculation precision, and reasonable processing speed. The proposed programmable architecture of CORDIC employs an interpreter and a programmable CORDIC iterator. These approaches can dynamically self-regulate the hardware function for calculating 15 different mathematical functions without any hardware modification. The implemented results prove that the proposed architecture is suitable for accelerating an embedded processor.

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