The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter sensitivity via bifurcation diagrams. Subsequently and despite the large number of parameters and large number of multiplication (or division) operations, these models are efficiently implemented on FPGA platforms using fixed-point architectures. Detailed FPGA design process, hardware architecture and timing analysis are provided for three of the studied models (Ebola, Influenza, and Cancer) on an Altera Cyclone IV EP4CE115F29C7 FPGA chip. All models are also implemented on a high performance Xilinx Artix-7 XC7A100TCSG324 FPGA for comparison of the needed hardware resources. Experimental results showing real-time control of the chaotic dynamics are presented.
Real-time classification of internet traffic is critical for the efficient management of networks. Classification approaches based on machine learning techniques have shown promising results with high levels of accuracy. In this paper, the suitability of packet-level and flow-level features is validated using stepwise regression and random forest feature selection. Moreover, the optimal percentage of packets considered within a flow while extracting flow-level features is determined. Several experiments are conducted using naïve Bayes, support vector machine, k-nearest neighbor, random forest, and artificial neural networks on the University of Brescia (UNIBS) and the University of New Brunswick (UNB) datasets, which are both publicly available. The performed experiments show that 60% of flow packets are a good compromise that ensures high performance in the least processing time. The results of the conducted experiments indicate that random forest outperforms other algorithms achieving a maximum accuracy of 98.5% and an F-score of 0.932. Further, and since software-based classifiers cannot meet the anticipated real-time requirements, we propose a Field-Programmable Gate Array (FPGA) based random forest implementation that utilizes a highly pipelined architecture to accelerate such a time-consuming task. The proposed design achieves an average throughput of 163.24 Gbps, exceeding throughputs of reported hardware-based classifiers that use comparable approaches, which in turn ensures the continuity of realtime traffic classification at congested data centers.
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