The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
Error correcting codes constitute one of the core technologies in telecommunications field, especially digital communication applications. The objective of this paper is to compare performance among new designs of chien search block on the one hand and syndrome architectures on the other hand in error correcting codes. All comparison of all designs is made by computing the number of logic, bit error rate values and number of iteration in the case of syndrome architectures Analysis results show that the performances of the new designs based on both second factorization method and Three-Parallel Syndrome architecture are superior to the performances of traditional designs.
In this paper, a new syndrome block for Reed Solomon RS and BCH codes used respectively in digital Video broadcasting DVB-S and DVB-S2 has been presented in order to reduce the number of iterations compared to the existed block, which can be found in the literature, the new method is based on a factorization of the equation corresponds to the syndrome block, which allows us to conceive another circuit. However, this reduction can approximately attain 40%. First, we developed and concepted the design of the proposed algorithm. Second, we transformed the circuits on hardware description language VHDL and finally we generated and simulated the basic and proposed algorithms using Quartus software tools.
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