Abstract:This letter presents a current-shaping technique for static MOS current-mode logic (MCML) prescalers. Simply with two extra current-shaping capacitors the self-oscillating frequecy is increased. A current vector model is also presented to illustrate the principles. The prescaler with the current-shaping technique was fabricated in a 0.18-μm CMOS technology with a reference classic one. The measurement results show that the self-oscillating frequency of the prescaler with current-shaping achieves an improvement of 10%, resulting a 6 GHz highest operating frequency while the classic one could only work at 5.3 GHz. Consequently, the current-shaping technique improves the maxim divide range of the prescaler with 13.2%. Keywords: current-mode logic, prescaler, current-shaping Classification: Integrated circuits References[1] M. Alioto, R. Mita, and G. Plumbo, "Design of high-speed power-efficient MOS current-mode logic frequency dividers," IEEE Trans. Circuits Syst.
An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 m CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 300 m 2 .
A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator (LDO). The pulsewidth-modulation (PWM) control method is adopted for better noise performance. An improved low-power highfrequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 A by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.
An output amplitude configurable wideband automatic gain control (AGC) with high gain step accuracy for the GNSS receiver is presented. The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs. And what's more, the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy. A zero, which is composed by the source feedback resistance and the source capacity, is introduced to compensate for the pole. The AGC is fabricated in a 0.18 μm CMOS process. The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB. The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA, and the die area is 800 × 300 μm2.
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