We investigated machine learning-based joint banknote recognition and counterfeit detection method. Unlike existing methods, since the proposed method simultaneously recognize banknote type and detect counterfeit detection, it is significantly faster than existing serial banknote recognition and counterfeit detection methods. Furthermore, we propose an explainable artificial intelligence method for visualizing regions that contributed to the recognition and detection. Using the visualization, it is possible to understand the behavior of the trained machine learning system. In experiments using the United State Dollar and the European Union Euro banknotes, the proposed method shows significant improvement in computation time from conventional serial method.
In general, a detailed modeling and evaluation of computer architectures make a cycleaccurate simulator necessary. As the architectures become increasingly complex for parallel, cloud, and neural computing, nowadays, the complexity of the simulator grows rapidly, and thus its execution is too slow or infeasible for practical use. In order to alleviate the problem, many previous studies have focused on reducing the simulation time in a variety of ways such as using sampling methods, adding hardware accelerators, and so on. In this paper, we propose a new parallel simulation framework, called Epoch-based Parallel SIMulator, to obtain scalable speedup with large number of cores. The framework is based on a well-known cycle-accurate full-system simulator, MARSSx86. From the simulator, we build an epoch, that is an execution interval, where the architectural simulation by PTLSim does not involve any interaction with QEMU. Therefore, we can simulate epochs independently, i.e., execute multiple epochs completely in parallel by PTLSim with their live-in data. Our performance evaluation shows that we achieve 12.8× speed on average with 16-core parallel simulation from the SPEC CPU2006 benchmarks and the PARSEC benchmarks, providing the performance scalability.
This letter proposes a novel sub-1 V voltage-current (V-I ) converter-based voltage-controlled oscillator (VCO) for the low-voltage phaselocked loop (PLL) of display driver integrated circuit. The proposed VCO improves on the state-of-the-art V-I converter-based VCO, which uses a firstorder current equation for the VCO, to achieve linear voltage-to-frequency gain of the VCO (K VCO ) over the full range of the control voltage, from the ground to the supply voltage in sub-1 V CMOS technology. To obtain a full supply transition output with high immunity to noise, the improved VCO is designed to control the gate voltage of a metal-oxide-semiconductor fieldeffect transistor (MOSFET), instead of the supply voltage of a ring oscillator without significant area overhead. As a result, the proposed VCO obtains a linear K VCO with a wider control voltage range than a conventional VCO when its tuning range is from 1.25 to 3.6 GHz in a 65 nm 1.0 V CMOS technology.
Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.
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