Organic semiconductors (OSCs) are highly susceptible to the formation of metastable polymorphs that are often transformed by external stimuli. However, thermally reversible transformations in OSCs with stability have not been achieved due to weak van der Waals forces, and poor phase homogeneity and crystallinity. Here, a polymorph of a single crystalline 2,7‐dioctyl[1] benzothieno[3,2‐b][1]benzothio‐phene rod on a low molecular weight poly(methyl methacrylate) (≈120k) that limits crystal coarsening during solvent vapor annealing is fabricated. Molecules in the polymorph lie down slightly toward the substrate compared to the equilibrium state, inducing an order of greater resistivity. During thermal cycling, the polymorph exhibits a reversible change in resistivity by 5.5 orders with hysteresis; this transition is stable toward bias and thermal cycling. Remarkably, varying cycling temperatures leads to diverse resistivities near room temperature, important for nonvolatile multivalue memories. These trends persist in the carrier mobility and on/off ratio of the polymorph field‐effect transistor. A combination of in situ grazing incident wide angle X‐ray scattering analyses, visualization for electronic and structural analysis simulations, and density functional theory calculations reveals that molecular tilt governs the charge transport characteristics; the polymorph transforms as molecules tilt, and thereby, only a homogeneous single‐crystalline phase appears at each temperature.
An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μ m CMOS process.
A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply.
This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The current-mode scheme prevents signal attenuation caused by source termination resistors, and it enhances signal power efficiency. On top of that, an adaptive amplitude tuning is implemented to mitigate non-linearity and closed-loop gain variations against load impedance variations. The proposed line driver achieves 87.0% power-efficiency and total harmonic distortion, plus noise (THD+N) of −49.0 dB at an input frequency of 40 MHz and output swing of 2.8 VPP differential. The adaptive amplitude tuning allows load impedance variations from 80 Ω to 160 Ω. The total power consumption is 37.6 mW with a 1.8 V supply voltage in 180 nm CMOS, and it occupies 0.377 mm2.
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