This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m) and 140 MHz (0.25 m).
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (CUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.
A linearly graded band gap design in the intrinsic layer of a p-i-n solar cell is studied numerically. An ideal model using Matlab ® is built and the device performance is calculated using continuity equations and an effective band gap model under various band gap combinations. The power conversion efficiency (PCE) can be as high as 30.21%, while the abrupt junction reference device only exhibits 29.25% under the same parameters. This design is also evaluated using the commercial TCAD software APSYS ® , and the calculations show optimal efficiency enhancements of about 1.14-fold that of the abrupt junction device in an AlAs/GaAs system and 2.05-fold that in an InGaN/GaN system.
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