Thermal monitoring is essential in integrated circuit (IC) and VLSI chip which are a multilayer structure and a stack of different materials. The increase of the internal temperature of the VLSI circuits can conduct to serious thermal and also thermo-mechanical problems. Due to aggressive technology scaling, VLSI integration density as well as power density increases drastically. Thermal phenomena research activities on micro-scale level are essential for SoC and MEMS-based applications. However, various measurement techniques are needed to understand the thermal behavior of VLSI chip. In particular, measurement techniques for surface temperature distributions of large VLSI systems are a highly challenging research topic. This paper presents an algorithm and the experimental result of silicon-die thermal monitoring method using embedded sensor cells unit. Sensor implementation results and analysis are also presented.
In this paper, we describe a new silicon-die thermal monitoring approach using spatiotemporal signal processing technique for Wafer-Scale IC thermomechanical stress monitoring. It is proposed in the context of a wafer-scale-based (WaferIC TM) rapid prototyping platform for electronic systems. This technique will be embedded into the structure of the WaferIC, and will be used as a preventive measure to protect the wafer from possible damages that can be caused by excessive thermomechanical stress. The paper also presents spatial and spatiotemporal algorithms and the experimental results from an IR images collection campaign conducted using an IR camera.
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