Some mobile applications require non volatile memories and very small spatial dimensions. The investigation results discussed in this paper are related to a via-last TSV integration scheme where a standard flash memory is connected to the backside of a processor chip (PC) using the through silicon via (TSV) technology. Special focus was given to the realization of chip interconnects between processor chip and the memory. This paper presents the process of the TSV formation starting with a photo resist deposition till TSV fill realized by electro-chemical copper deposition (ECD) and briefly the manufacturing of the redistribution layers as well the die-to-wafer (D2W) assembly of the flash chips. Electrical results will be presented showing the quality of the TSV isolation, the effect of the TSVs on its adjacencies and the quality of the interconnects for the case of flash chips attached to the frontside of the processor wafer (PW)
In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 mu m holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone
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