2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fullydepleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS 2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable V T by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.
Molybdenum
trioxide (MoO3), an important transition
metal oxide (TMO), has been extensively investigated over the past
few decades due to its potential in existing and emerging technologies,
including catalysis, energy and data storage, electrochromic devices,
and sensors. Recently, the growing interest in two-dimensional (2D)
materials, often rich in interesting properties and functionalities
compared to their bulk counterparts, has led to the investigation
of 2D MoO3. However, the realization of large-area true
2D (single to few atom layers thick) MoO3 is yet to be
achieved. Here, we demonstrate a facile route to obtain wafer-scale
monolayer amorphous MoO3 using 2D MoS2 as a
starting material, followed by UV–ozone oxidation at a substrate
temperature as low as 120 °C. This simple yet effective process
yields smooth, continuous, uniform, and stable monolayer oxide with
wafer-scale homogeneity, as confirmed by several characterization
techniques, including atomic force microscopy, numerous spectroscopy
methods, and scanning transmission electron microscopy. Furthermore,
using the subnanometer MoO3 as the active layer sandwiched
between two metal electrodes, we demonstrate the thinnest oxide-based
nonvolatile resistive switching memory with a low voltage operation
and a high ON/OFF ratio. These results (potentially extendable to
other TMOs) will enable further exploration of subnanometer stoichiometric
MoO3, extending the frontiers of ultrathin flexible oxide
materials and devices.
CMOS technology for 1.2V high performance applications is being scaled to sub-0.09pm physical nominal gate lengths and with effective gate dielectric thickness less than 2nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09pm (post gate reoxidation), and gate dielectric thickness of 2.7nm (nMOS), 3.0nm (PMOS) (inversion at 1.2V), nMOS and PMOS Idrive is 763 pA/pm and 333 pA/pm respectively, at 1.2V with maximum Ioff=5nA/pm. Gate-drain overlap in this work is -2 10 h i d e and bottomwall junction capacitance is reduced to 0.8 fF/pm2 (PMOS) and 1.1 fF/Fm2 (nMOS). With reduced parasitics and high drive current, the 1.2V technology FOM (Figure-of-Merit) is > 39GHz, meeting the roadmap trend.
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