CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also
For
realizing Ge CMOS devices with a small equivalent oxide thickness
(EOT) and a low density of fast interface states (D
it), understanding of slow traps in Ge gate stacks and
reduction of its density are one of the most crucial issues. For this
purpose, we examine slow trap density and locations of Al2O3/GeO
x
/Ge MOS gate stacks,
which are fabricated by plasma oxidation in this work. In Al2O3/GeO
x
/Ge MOS interfaces
formed by preplasma oxidation (pre-PO) and postplasma oxidation (post-PO),
slow trap density has been compared. Also, the slow trap density on
the thickness dependence of GeO
x
and Al2O3 is systematically evaluated for the Al2O3/GeO
x
/Ge MOS gate stacks
formed by pre-PO. It is found that near the conduction band edge of
Ge, additional electron slow traps will be generated by using the
post-PO process. Above all, in the Al2O3/GeO
x
/Ge MOS interfaces with pre-PO. The main
slow traps can be located near the GeO
x
/Ge interfaces for the electrons and the Al2O3/GeO
x
interfaces for the holes, respectively.
The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (Dit) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al2O3/GeOx/n-Ge and HfO2/Al2O3/GeOx/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al2O3 and HfO2/Al2O3 combined with plasma post oxidation. It is found that the slow traps can locate in the GeOx interfacial layer, not in the ALD Al2O3 layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al2O3/GeOx/Ge gate stacks, with changing the thickness of GeOx, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeOx, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeOx.
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