[Bi2O2]-containing tetragonal compounds have received enormous attention due to unique functions including ferroelectricity, photocatalysis, and superconductivity. Here, a new layered compound Bi9O7.5S6 was synthesized via a facile hydrothermal route. The compound, belonging to a new structure type crystallizes in a rhombohedral system with space group R3̅m (a = 4.0685(1) Å, c = 31.029(5) Å, V = 444.8(1) Å(3), Z = 1). The overall crystal structure consists of alternatively packed unique [Bi2O2] and [BiS2] layers along [001] which are combined with each other by van der Waals interaction. The phase purity of the product is confirmed by powder X-ray diffraction. XPS analyses indicate +3 for Bi and -2 for S atoms. The temperature dependence of resistivity ρ(T) indicates that the semiconducting sample follows the mechanisms of variable range hopping (VRH) and adiabatic small polaron hopping (SPH). The direct-transition band gap, Eg = 1.27 eV derived from optical absorption spectrum, falls in the optimal region of solar absorber materials. Accordingly, the photoelectric measurement demonstrates the potential for applications for photovoltaic devices.

Software-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming unable to meet the requirements of high-speed packet processing. FPGAs are usually used as dumb switches to accelerate the data plane, with all intelligence centralized in the remote controller. However, the cost of taking the intelligence out of the switch is the increased latency between the controller and the switch. Therefore, we argue that the control decisions should be made as locally as possible. In this paper, we propose a novel architecture with high performance and flexibility for accelerating SDN based on the MPSoC platform. The control plane is implemented in the on-chip CPU and the data plane is implemented in the FPGA logic. The communication between the two components is performed using Ethernet communication. We design a high-performance TCAM based on distributed RAM. The architecture employs a pipeline design with modules connected via the AXI Stream interface. The designed architecture is flexible enough to support multiple network functions while achieving high performance at 100 Gbps. As far as we know, the architecture is the first proposed in the design of a 100 Gbps system.

In order to facilitate the transition between networks and the integration of heterogeneous networks, the underlying link design of the current mainstream Information-Centric Networking (ICN) still considers the characteristics of the general network and extends the customized ICN protocol on this basis. This requires that the network transmission equipment can not only distinguish general network packets but also support the identification of ICN-specific protocols. However, traditional network protocol parsers are designed for specific network application scenarios, and it is difficult to flexibly expand new protocol parsing rules for different ICN network architectures. For this reason, we propose a general dynamic extensible protocol parser deployed on FPGA, which supports the real-time update of network protocol parsing rules by configuring extended protocol descriptors. At the same time, the multi-queue protocol management mechanism is adopted to realize the grouping management and rapid parsing of the extended protocol. The results demonstrate that the method can effectively support the protocol parsing of 100 Gbps high-speed network data packets and can dynamically update the protocol parsing rules under ultra-low latency. Compared with the current commercial programmable network equipment, this solution improves the protocol update efficiency by several orders of magnitude and better supports the online updating of network equipment.