In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate off-voltage, the reset gate off-voltage, the photodiode integration time, and the sense node charge retention time. Besides the well-known source follower RTN, we have identified the RTN caused by varying photodiode dark current, transfer-gate and reset-gate induced sense node leakage. These four types of RTN and the dark signal shot noises dominate the noise distribution tails of CIS and non-CIS chips under test, either with or without X-ray irradiation. The effect of correlated multiple sampling (CMS) on noise reduction is studied and a theoretical model is developed to account for the measurement results.
Accurate simulation of today's devices needs to account for real device geometry complexities after the lithography and etching processes, especially when the channel length shrinks to 65-nm and below. The device performance is believed to be quite different from what designers expect in the conventional IC design flow. The traditional design lacks consideration of the photolithography effects and pattern geometrical operations from the manufacturing side. In to order obtain more accurate prediction on circuits, an efficient approach to estimate nonrectangular MOSFET devices is proposed. In addition, an electrical hotspot criterion is also proposed to investigate and verify the manufacturability of devices during patterning processes. This electrical rule criterion will be performed after the regular Design Rule Check (DRC) or Design for Manufacturing (DFM) rule check. Photolithography and industrial-strength SPICE model are taken into consideration to further correlate the process variation. As a result, the correlation between process-windows and driving current variation of devices will be discussed explicitly in this paper.
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