A B S T R A C TRemote sensing applications in agriculture are presented as a very promising reality, but research is still needed for the correct use of spectral data. The objective of this study was to evaluate the spectral-temporal patterns of eleven wheat cultivars (Triticum aestivum L.). The experiment was conducted in Cascavel, PR, in the year 2014. With the help of the GreenSeeker and FieldSpec 4 terrestrial sensors, spectral signatures were determined and the temporal profiles of the Normalized Difference Vegetation Index (NDVI) were created. Statistical differences between wheat cultivars were analysed using analysis of variance (ANOVA) and Scott-Knott test. Grain yields obtained with INSEY (In-Season Estimate of Yield) factors were correlated. NDVI normalized by degree-days accumulated from the Feekes growth stages 2 and 8 showed to be more consistent in the estimation of grain yield, explaining approximately 70% of the variation. At the Feekes stage 10.1, wheat cultivars presented different spectral patterns in the near and medium infrared bands. This suggests that these spectral bands can be used to differentiate wheat cultivars.
The design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the decisions in the design exploration cycle with high flexibility and reduced cost. The increasing system complexity makes the traditional approach to simulation inefficient for today's architectures. The compiled simulation technique makes use of a priori knowledge about the application to accelerate the simulation with high efficiency. This paper presents a retargetable compiled simulator with three optimization techniques and taking advantage of new GCC optimizations to improve the performance. Three architectures were modeled and tested, MIPS, SPARC and PowerPC. Our MIPS model achieved the best results, with average of 651 million instruction per second, and only 2.8 times slower than native execution.
Current microprocessors spend a huge percentage of the die area to implement the memory hierarchy. Moreover, cache memory is responsible for a significant percentage of the total energy consumption. This paper presents a novel data cache design to reduce its die area, power dissipation and latency. The new scheme, called Non Redundant Cache (NRC), exploits the immense amount of value replication observed in traditional data caches. The NRC cache significantly reduces the storage requirements by avoiding the replication of values. Results show that the NRC cache reduces the die area in a 32%, the power dissipation by 14% and the latency by 25%, while maintaining the miss ratio of a conventional cache.
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