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In this paper, an advanced 40nm, Cu/low-K 22x18mm 2 Si chip with 42.5x42.5mm 2 flip chip BGA-1681L package was used with substrate core material split on CTE ~12ppm vs. 17ppm, and underfill material split on high Tg vs. low Tg. The packages were mounted on PWB (printed wiring board) for second-level interconnect SAC405 BGA reliability characterization. Thermal heaters and sensors were built-in the chip with first-level and second-level interconnect daisy chain designs to enable power cycling and thermal cycling reliability characterization.Experiments with variety of temperature range were conducted to compare second-level interconnects reliability under power cycling and thermal cycling tests. The results showed that thermal cycling with 25~125°C profile could accelerate the test compared with 0~100°C and reflected the similar failure ball location in the die-shadow edge as that from power cycling test. However, the typical thermal cycling ranging between 0°C and 100°C showed different worst cracked balls location around the package edge. An acceleration stress methodology for second-level interconnects reliability had been established on power cycling by increasing temperature ramp rate and raising peak temperature, while still keeping the same failure phenomenon. Underfill Tg effect was observed on solder fatigue performance that high Tg underfill resulted in shorter fatigue cycle. Failure analysis was performed to understand the failure mode and failure location differences. A non-linear 3-D board-level finite-element analysis (FEA) was carried out to characterize the second-level interconnect BGA strain distribution difference under power cycling and thermal cycling tests with underfill and substrate core material splits. IntroductionExtreme low-k dielectric materials have been implemented in backend interconnects for electrical performance improvement in advanced Si technologies, including 40nm, 28nm, and beyond. At the same time, more functionality is integrated into a single chip, which makes the die size larger and I/O density higher that require finer C4 bump pitch and larger package body size. Accompanied with the lead-free solder bump transition, these combined factors are driving more challenging CPI (Chip package interaction). As a result, low CTE (coefficient of thermal expansion) substrate is introduced to reduce the thermo-mechanical stress induced by CTE mismatch between Si and organic substrate, and high Tg (glass transition temperature) underfill is also required to protect lead-free solder bumps from cracks. However, the low CTE substrate and high Tg underfill have theoretically negative impact on second-level interconnects fatigue.

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