This study aims to benchmark and analyze the process development and manufacturing costs across the biopharmaceutical drug development cycle and their contribution to overall research and development (R&D) costs. This was achieved with a biopharmaceutical drug development lifecycle cost model that captured the costs, durations, risks and interdependencies of the clinical, process development and manufacturing activities. The budgets needed for process development and manufacturing at each phase of development to ensure a market success each year were estimated. The impact of different clinical success rate profiles on the process development and manufacturing costs at each stage was investigated, with a particular focus on monoclonal antibodies. To ensure a market success each year with an overall clinical success rate (Phase I to approval) of 12%, the model predicted that a biopharmaceutical company needs to allocate process development and manufacturing budgets in the order of~$60 M for pre-clinical to Phase II material preparation and~$70 M for Phase III to regulatory review material preparation. For lower overall clinical success rates of~4%, which are more indicative of diseases such as Alzheimer's, these values increase to~$190 M for early-phase and~$140 Mfor late-phase material preparation; hence, the costs increase 2.5 fold. The costs for process development and manufacturing per market success were predicted to represent 13-17% of the R&D budget from pre-clinical trials to approval. The results of this quantitative structured cost study can be used to aid decision-making during portfolio management and budget planning procedures in biopharmaceutical development.

With the introduction of new generations of Systems on Chip (SoC) on 0.18 µm and 0.12µm technologies, the production cost and time to volume become more and more critical, on top of best in class level of quality and reliability. The SoC approach -widely based on the usage of cell libraries or reusable IP blocks -brings extreme complexity. Accurate knowledge and level of validation on silicon of each block of library/IP used within new chip becomes mandatory in order to secure first silicon success.In this context, knowledge sharing between users of the same IP in different SoC plays a key role in cost optimisation & time to volume reduction. This paper describes the information system solution developed on 0.18µm technology, named LYS (Library Yield System). LYS allows keeping track of the version of library cells or reusable IP blocks used within each SoC of a given technology. Each SoC project is analysed at different steps of its life cycle starting from product specification up to silicon qualification. Block by block silicon results applied to SoC, and early warning system linking the different projects together, allow to optimise and update in real time the content of each projects, and to perform the needed improvements.This methodology allows, before mask order, any new project to be updated with appropriate library or IP blocks revision in order to get rid of known silicon issues detected on previous projects. This solution is now fully implemented and in use on 0.35µm, 0.25µm, 0.18µm, 0.12µm, and 90nm technologies.As far as we know, there is no equivalent solution available & running in microelectronics companies.This solution (LYS) has already proven to be mandatory for all new technologies: the content (in terms of cell libraries and IP blocks) of more than 60% of the 0.18µm products were optimised thanks to LYS. These optimisations mainly covered library design robustness and yield maximization. We can today estimate that several months were saved in time to volume for the 0.18µm production.

Designers can create completely new processors with custom instruction set architectures (ISA), using various methods involving configurable logic. Configurable technologies also enable designers to enhance the basic ISA of standard processors or the ISA of a proprietary processor to execute at speed workloads for which the processor has not been initially conceived. Contrary to some early beliefs, the idea behind creating a custom instruction is not to compress several existing ISA instructions in one cycle; it is to execute loops requiring hundreds or thousands of iterations, faster than in a single machine, even if it were clocked at the top frequency afforded by state-of-the-art semiconductor speeds and temperature limitations.To achieve high performance, most configurable platforms execute loop iterations in parallel; operating on multiple data in one cycle can make up for engine frequency and power limitations. Aimed at implementations in ASIC technologies, configurable platforms can be defined as designer-created mostly hardwired logic interfaced via ISA instruction enhancements Re-configurable platforms were introduced only recently. Architectures employing FPGA-like structures instead of hardwired logic offer flexibility useful in addressing a broader range of applications and tracking evolving standards. The presentation surveys configurable and re-configurable structures including fabrics of processors, evolving trends, and the impact of soft-hardware development tools.Fabrics of processors were initially aimed at very high performance tasks in communications. This type of architecture is also beginning to be employed in low power applications where it can offer a ratio of performance-to-power exceeding that of an implementation using one or more general-purpose processors. Several emerging fabric configurations will be described and compared: base cores using a processor element (PE) and private memory for instructions and data, PEs using local instructions' memory and communicating data, PEs that can change processing capabilities depending on the function to be executed, heterogeneous PEs and others. Software development tools' issues have kept processor fabrics from being adopted by more designers: iterative optimal routing between PEs and assignment of functions have become additional burdens on the C/C++ language programmer. None of the proposed products has acquired enough traction to justify acceptance as a standard architecture. The key to a wider adoption of re-configurable engines will be found in the soft-hardware tools offered to the programmer: two types of soft-hardware tools will be described, one using program and explicit routing, the other employing hints that can generate program and routing.

There was a time -in the dim historical past -when foundries actually made ASICs with only 5000 to 50,000 logic gates. But FPGAs and CPLDs conquered those markets and pushed ASIC silicon toward opportunities with more logic, volume, and speed. Today's largest FPGAs approach the few-million-gate size of a typical ASIC design, and continue to sprout embedded cores, such as CPUs, memories, and interfaces. And given the risks of nonworking nanometer silicon, FPGA costs and time-to-market are looking awfully attractive. So, will FPGAs kill ASICs? ASIC technologists certainly think not. ASICs are themselves sprouting patches of programmable FPGA fabric, and pushing new realms of size and especially speed. New tools claim to have tamed the convergence problems of older ASIC flows. Is the future to be found in a market full of FPGAs with ASIC-like cores? ASICs with FPGA cores? Other exotic hybrids? Our panelists will share their disagreements on these prognostications.