System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for embedded real-time signal processing because of their high performance and low latency. Here we describe the process of implementing the Open Master Hearing Aid [1] on an SoC FPGA. We started by creating a FFT based Simulink model to implement hardware friendly frequency-domain processing. This model implements Short-Time Fourier Transform processing in an overlap-and-add architecture. This was followed by porting additional openMHA processing blocks, such as dynamic range compression, to Simulink. Once the hearing aid Simulink model was finished, Mathwork's HDL Coder was used to create VHDL. To create an interactive system, we used Audio Logic's code generation tools to generate the infrastructure needed to communicate with the hearing aid processor in real-time; this includes generating device drivers that allow Linux to communicate with the hearing aid processor, as well as a custom web application with an autogenerated GUI. This example provides an open reference design for those who may be interested in low latency FPGA based data flow architectures. 1. www.openmha.org
System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for real-time signal processing due to their low, deterministic latency and high performance. To showcase the utility of our open FPGA computational platform for real-time audio signal processing and computational modeling, several applications have been implemented. We have ported the openMHA hearing aid software [1] to our platform to show that pre-existing audio processing software can be implemented in SoC FPGAs by making external audio interfaces show up as a sound card. To highlight the ability to perform real-time computational modeling on our performance platform, we are implementing a real-time version of Laurel Carney’s auditory-nerve model [2] running in its own custom accelerator in the FPGA fabric. To illustrate the ability to develop DSP algorithms in MathWork’s Simulink and then implement them in the FPGA fabric we have taken several algorithms from Issa Panahi’s group [3] to show both frame-based processing (noise reduction) and sample-based processing (dynamic range compression). Finally, we show that the platform can be used to visualize audio signals using a real-time spectrogram where FFTs are computed in the FPGA fabric. [1] www.openmha.org. [2] JASA 126, 2390–2412. [3] www.utdallas.edu/ssprl/hearing-aid-project/.
System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for real-time signal processing due to their low, deterministic latency and high performance. We target our Audio Blade platform that contains an Intel Arria 10 SoC FPGA with floating-point capability and 1.5 TFLOPS performance. In order to target the Arria 10, the auditory nerve model [1, 2] needed to be ported to a hardware description language. We accomplished this by first porting the MATLAB/C model to Simulink, and then used MathWorks HDL Coder to generate VHDL code. Our hardware-accelerated model will allow researchers to edit model parameters in real-time from Linux software running on the embedded ARM CPUs and view the resulting nerve responses in real-time. The goal is to create a real-time platform running multiple auditory nerve models, allowing researchers to inject hearing impairments and then develop hearing aid strategies to compensate for these hearing deficits. We will discuss performance measures of the FPGA-based auditory nerve models, including latency measures and how many auditory nerve models can run simultaneously in the Arria 10 FPGA fabric. 1. Bruce et al., Hearing Res. 360, 40–54 (2018). 2. Zilany et al., JASA 126, 2390–2412 (2009).
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