A common approach to the modeling of temperature evolution in a multi-zone building is to use thermal resistance and capacitance to model zone and wall dynamics. The resulting thermal network may be represented as an undirected graph. The thermal capacitances are the nodes in the graph, connected by thermal resistances as links. The temperature measurements and temperature control elements (heating and cooling) in this lumped model are collocated. As a result, the input/output system is strictly passive and any passive output feedback controller may be used to improve the transient and steady state performance without affecting the closed loop stability. The storage functions associated with passive systems may be used to construct a Lyapunov function, to demonstrate closed loop stability and motivate the construction of an adaptive feedforward control to compensate for the variation of the ambient temperature and zone heat loads (due to changing occupancy). The approach lends itself naturally to an inner-outer loop control architecture where the inner loop is designed for stability, while the outer loop balances between temperature specification and power consumption. Energy efficiency consideration may be added by adjusting the target zone temperature based on user preference and energy usage. The initial analysis uses zone heating/cooling as input, but the approach may be extended to more general model where the zonal mass flow rate is the control variable. A fourroom example with realistic ambient temperature variation is included to illustrate the performance of the proposed passivity based control strategy. I. INTRODUCTIONHeating, ventilation, and air conditioning (HVAC) system is a major energy consumer in buildings. For the analysis of building temperature evolution under HVAC control, a common approach is to model it as an interconnected network of lumped thermal capacitors and resistors. Thermal resistance models the heat flow due to temperature difference: Q = ∆T /R, where Q (in W) is the rate of heat transfer across the resistance, ∆T is the temperature difference (in K), and R is the thermal resistance (K/W). Thermal capacitance (or thermal mass) models the ability of a space (or wall) to store heat: C d∆T dt = Q,where C has the unit J/K. We model a single zone as a single thermal capacitor and use the standard 3R2C model [1] for the wall (i.e., the wall is characterized by three thermal resistors in series shunted by two thermal capacitors at the nodes). As shown in [2], the temperature dynamics of a thermal RC network modeled as a graph consisting of n nodes (capacitors) and links (resistors) is given by where C ∈ R n×n is a diagonal, positive definite matrix consisting of the thermal capacitances, R ∈ R × is a diagonal, positive definite matrix consisting of the link thermal resistances, D ∈ R n× is the incidence matrix of the graph, B 0 = −DR −1 d T 0 ∈ R n is a column vector with non-zero elements as the thermal conductance of nodes connected to the ambient, T ∞ is the ambient temperature, u ∈ R...
A set of measurement techniques-SILC, low frequency noise, and pulse CV -combined with the physical descriptions of the processes associated with these measurements were applied to study pre-existing and stress generated traps in the SiO 2 /HfO 2 gate stacks. By correlating the analysis results obtained by these techniques, the defects in the high-k dielectric and interfacial layer were identified. The stress-induced degradation of the high-k gate stack was found to be caused primarily by the trap generation in the SiO 2 interfacial layer.
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